1. Field of the Invention
The present invention relates in general a buffer memory for a network switch port for receiving, storing and thereafter reading out and forwarding cells derived from network data transmissions, and in particular to a buffer manager that selects an order in which cells are written into and read out of buffer memory banks in a manner that optimizes memory access rates.
2. Description of Related Art
A network switch routes data transmissions such as ethernet packets between network buses. A typical network switch includes a set of input ports for receiving packets arriving on the buses, a set of output ports for forwarding packets outward on the buses, and a switch fabric such as a crosspoint switch for routing packets from each input switch port to the output switch ports that are to forward them.
Network switch input and output ports often include buffer memories for storing packets until they can be forwarded thorough the switch fabric or outward on a network bus. Since packets may be of variable size, an input port may convert each packet arriving on a network bus to a sequence of cells of uniform size which can be efficiently stored in uniformly-sized buffer memory storage locations. The input port stores the cells of each sequence in its buffer memory until it can forward them through the switch fabric to one of the switch""s output ports. The output switch port stores the cells in its buffer memory and later reads them out, reassembles them into the packet from which they were derived, and then forwards the packet outward on another network bus.
A network switch port often uses one or more synchronous dynamic random access memories (SDRAMs) to implement its buffer memory because large SDRAMs capable of storing many cells are inexpensive. An SDRAM may include more than one memory bank, and the switch port""s buffer manager can read or write access a cell stored at an address within any one of those memory banks, for example, in four cycles of a system clock signal. Also such an SDRAM may require, for example, an extra two cycles recovery time when switching from a read access to a write access or vice-versa, even when the accesses are to different banks. However this does not mean that the buffer manager can read or write access the SDRAM every four or six clock signal cycles. Once the buffer manager read or write accesses any address of an SDRAM memory bank, the buffer manager must allow that bank a certain amount of additional time to recover (precharge) before the buffer manager can read or write access any address of that SDRAM bank again. For example an SDRAM having a four cycle access time may require an additional six clock cycles to recover after a read access and an additional nine clock cycles to recover after a write access. Thus even though an SDRAM may have a four or six cycle access time, a buffer manager could repeatedly read access the same SDRAM bank only once every ten clock signal cycles and repeatedly write access the same SDRAM bank only once every 13 clock signal cycles.
When such an SDRAM has, for example, four memory banks A-D, a buffer manager could read or write access the SDRAM once every one four or six clock cycles if it were able to avoid read or write accessing any one bank more than once every 13 clock cycles. However since the cells stored in the buffer memory of a network switch are parts of sequences of cells derived from packets, the buffer manager must forward the cells of each sequence from the buffer memory in proper sequential order so that they can be properly reassembled into packets. That particular order may not be optimal with respect to rate at which they can be read out of the buffer memory. Since a conventional buffer manager for a network port would not be able to control the order in which it accesses the banks of such an SDRAM so as to optimize access rates, it would have to limit accesses to once every 13 clock cycles to make sure that it did not write access the same memory bank too frequently.
What is needed is a buffer manager for a network switch port that can order buffer memory bank accesses to optimize the rate at which it read and write accesses the buffer memory, but which nonetheless forwards cells read out of memory in an appropriate sequential order regardless of the order in which they were read out of the buffer memory.
A network switch port includes a buffer memory for storing cells derived from network data transmissions and a buffer manager for writing incoming cells into the buffer memory and for thereafter reading the cells out of the buffer memory and forwarding them elsewhere. The buffer memory includes several memory banks, and the rate at which the buffer manager is able to read and write accesses the buffer memory depends on the order in which the buffer manager read and write accesses those memory banks.
The switch port also includes a queue manager for determining an order in which the buffer manager is to forward cells stored in the buffer memory. To tell the buffer manager the order in which to forward a set of cells stored in the buffer memory, the queue manager supplies the buffer manager with a first sequence of read pointers, wherein each read pointer references a separate cell of the set of cells to be read out of the buffer memory. The queue manager orders the read pointers within the first sequence to indicate the order in which the buffer manager is to forward the cells.
In accordance with one aspect of the invention, the buffer manager processes the first sequence to produce a second sequence including all of the read pointers of the first sequence along with a set of write pointers. Each write pointer points to a separate address of buffer memory that is available for receiving an incoming cell. The buffer manager then read and write access the buffer memory in the order indicated by the write and read pointers of the second sequence.
In accordance with another aspect of the invention, the buffer manager orders the read and write pointers of the second sequence to optimize a rate at which it can read and write access buffer memory""s memory banks. Hence the read pointers do not necessarily appear in the second sequence in the same order that they appear in the first sequence. The buffer manager therefore does not necessarily read cells out of the buffer manager in the order in which the queue manager determined they are to be forwarded. However as it reads cells out of the buffer memory, the buffer manager stores them in a set of registers. The buffer manager thereafter reads the cells out of the registers and forwards them from the switch port manager in the order in which the queue manager determined they should be forwarded.
Thus the buffer manager orders buffer memory bank read and write accesses to optimize the rate at which it can read and write accesses the buffer memory, but nonetheless forwards the cells it reads out of the buffer memory in the appropriate sequential order specified by the queue manager.
It is accordingly an object of the invention to provide a system for optimizing the speed with which a buffer manager reads and write accesses cells stored in a buffer memory.
The concluding portion of this specification particularly points out and distinctly claims the subject matter of the present invention. However those skilled in the art will best understand both the organization and method of operation of the invention, together with further advantages and objects thereof, by reading the remaining portions of the specification in view of the accompanying drawing(s) wherein like reference characters refer to like elements.